<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
</tr>
<tr>
<td>Path</td>
<td>D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>D:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\Intel\iCLS Client\;<br>C:\Program Files\Intel\iCLS Client\;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>C:\WINDOWS\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\IPT;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\IPT;<br>D:\Program Files (x86)\IDM Computer Solutions\UltraEdit;<br>D:\Program Files\MATLAB\R2016a\runtime\win64;<br>D:\Program Files\MATLAB\R2016a\bin;<br>D:\Program Files\MATLAB\R2016a\polyspace\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Users\YZG\AppData\Local\Microsoft\WindowsApps;<br>D:\modeltech64_10.2\win64;<br>D:\intelFPGA_lite\16.1\modelsim_ase\win32aloem</td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>D:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\Intel\iCLS Client\;<br>C:\Program Files\Intel\iCLS Client\;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>C:\WINDOWS\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\IPT;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\IPT;<br>D:\Program Files (x86)\IDM Computer Solutions\UltraEdit;<br>D:\Program Files\MATLAB\R2016a\runtime\win64;<br>D:\Program Files\MATLAB\R2016a\bin;<br>D:\Program Files\MATLAB\R2016a\polyspace\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Users\YZG\AppData\Local\Microsoft\WindowsApps;<br>D:\modeltech64_10.2\win64;<br>D:\intelFPGA_lite\16.1\modelsim_ase\win32aloem</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>D:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\Intel\iCLS Client\;<br>C:\Program Files\Intel\iCLS Client\;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>C:\WINDOWS\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\IPT;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\IPT;<br>D:\Program Files (x86)\IDM Computer Solutions\UltraEdit;<br>D:\Program Files\MATLAB\R2016a\runtime\win64;<br>D:\Program Files\MATLAB\R2016a\bin;<br>D:\Program Files\MATLAB\R2016a\polyspace\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Users\YZG\AppData\Local\Microsoft\WindowsApps;<br>D:\modeltech64_10.2\win64;<br>D:\intelFPGA_lite\16.1\modelsim_ase\win32aloem</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>D:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>D:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\Intel\iCLS Client\;<br>C:\Program Files\Intel\iCLS Client\;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>C:\WINDOWS\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\IPT;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\IPT;<br>D:\Program Files (x86)\IDM Computer Solutions\UltraEdit;<br>D:\Program Files\MATLAB\R2016a\runtime\win64;<br>D:\Program Files\MATLAB\R2016a\bin;<br>D:\Program Files\MATLAB\R2016a\polyspace\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Users\YZG\AppData\Local\Microsoft\WindowsApps;<br>D:\modeltech64_10.2\win64;<br>D:\intelFPGA_lite\16.1\modelsim_ase\win32aloem</font></td>
</tr>
<tr>
<td>XILINX</td>
<td>D:\Xilinx\14.7\ISE_DS\ISE\</td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE\</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE\</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE\</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>D:\Xilinx\14.7\ISE_DS\ISE</td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\ISE</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>D:\Xilinx\14.7\ISE_DS\EDK</td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\EDK</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\EDK</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\EDK</font></td>
</tr>
<tr>
<td>XILINX_FOR_ALTIUM_OVERRIDE</td>
<td> </td>
<td><font color=gray> </font></td>
<td><font color=gray> </font></td>
<td><font color=gray> </font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>D:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\PlanAhead</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\PlanAhead</font></td>
<td><font color=gray>D:\Xilinx\14.7\ISE_DS\PlanAhead</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>online_lever.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>online_lever</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx9-2-tqg144</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>online_lever</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>16</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td><font color=gray>-intstyle</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>ise</font></td>
<td><font color=gray>None</font></td>
</tr>
<tr>
<td><font color=gray>-dd</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>_ngo</font></td>
<td><font color=gray>None</font></td>
</tr>
<tr>
<td><font color=gray>-p</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>xc6slx9-tqg144-2</font></td>
<td><font color=gray>None</font></td>
</tr>
<tr>
<td><font color=gray>-uc</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>E:/FPGA/26online_lever/ise/online_lever.ucf</font></td>
<td><font color=gray>None</font></td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td><font color=gray>-ol</font></td>
<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
<td><font color=gray>high</font></td>
<td><font color=gray>high</font></td>
</tr>
<tr>
<td><font color=gray>-xt</font></td>
<td><font color=gray>Extra Cost Tables</font></td>
<td><font color=gray>0</font></td>
<td><font color=gray>0</font></td>
</tr>
<tr>
<td><font color=gray>-ir</font></td>
<td><font color=gray>Use RLOC Constraints</font></td>
<td><font color=gray>OFF</font></td>
<td><font color=gray>OFF</font></td>
</tr>
<tr>
<td><font color=gray>-t</font></td>
<td><font color=gray>Starting Placer Cost Table (1-100) Map</font></td>
<td><font color=gray>1</font></td>
<td><font color=gray>0</font></td>
</tr>
<tr>
<td><font color=gray>-r</font></td>
<td><font color=gray>Register Ordering</font></td>
<td><font color=gray>4</font></td>
<td><font color=gray>4</font></td>
</tr>
<tr>
<td><font color=gray>-intstyle</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>ise</font></td>
<td><font color=gray>None</font></td>
</tr>
<tr>
<td><font color=gray>-lc</font></td>
<td><font color=gray>LUT Combining</font></td>
<td><font color=gray>off</font></td>
<td><font color=gray>off</font></td>
</tr>
<tr>
<td><font color=gray>-o</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>online_lever_map.ncd</font></td>
<td><font color=gray>None</font></td>
</tr>
<tr>
<td><font color=gray>-w</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>true</font></td>
<td><font color=gray>false</font></td>
</tr>
<tr>
<td><font color=gray>-pr</font></td>
<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td>
<td><font color=gray>off</font></td>
<td><font color=gray>off</font></td>
</tr>
<tr>
<td><font color=gray>-p</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>xc6slx9-tqg144-2</font></td>
<td><font color=gray>None</font></td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td><font color=gray>-intstyle</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>ise</font></td>
<td><font color=gray>&nbsp;</font></td>
</tr>
<tr>
<td><font color=gray>-mt</font></td>
<td><font color=gray>Enable Multi-Threading</font></td>
<td><font color=gray>off</font></td>
<td><font color=gray>off</font></td>
</tr>
<tr>
<td><font color=gray>-ol</font></td>
<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
<td><font color=gray>high</font></td>
<td><font color=gray>std</font></td>
</tr>
<tr>
<td><font color=gray>-w</font></td>
<td><font color=gray>&nbsp;</font></td>
<td><font color=gray>true</font></td>
<td><font color=gray>false</font></td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz/2494 MHz</td>
<td><font color=gray>Intel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz/2494 MHz</font></td>
<td><font color=gray>Intel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz/2494 MHz</font></td>
<td><font color=gray>Intel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz/2494 MHz</font></td>
</tr>
<tr>
<td>Host</td>
<td>DESKTOP-9CPDG88</td>
<td><font color=gray>DESKTOP-9CPDG88</font></td>
<td><font color=gray>DESKTOP-9CPDG88</font></td>
<td><font color=gray>DESKTOP-9CPDG88</font></td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft , 64-bit</td>
<td><font color=gray>Microsoft , 64-bit</font></td>
<td><font color=gray>Microsoft , 64-bit</font></td>
<td><font color=gray>Microsoft , 64-bit</font></td>
</tr>
<tr>
<td>OS Release</td>
<td>major release  (build 9200)</td>
<td><font color=gray>major release  (build 9200)</font></td>
<td><font color=gray>major release  (build 9200)</font></td>
<td><font color=gray>major release  (build 9200)</font></td>
</tr>
</TABLE>
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